1. Field of the Invention
The present invention relates to video display apparatus, and more particularly to such apparatus comprising a series of data processors concurrently operating in parallel to provide real time display of a video picture in accordance with a selected signal processing algorithm; for example, a signal processing algorithm which is to be evaluated.
2. Description of the Related Art
Product life cycles of video display apparatus are continually falling with the rapid advent of new and improved features of video signal processing circuits, and the resulting additional complexity of such circuits increases the development time, cost and risk to the supplier. In order to minimize this, computer-aided simulation is employed to simulate the effect on a video picture of various possible signal processing algorithms which are to be evaluated. The video signal corresponding to the series of raster images (fields or frames) which form the picture is processed by a computer programmed to execute an algorithm which is functionally equivalent to the combination of signal processing circuits employed in the actual video display apparatus, and the so-processed signal is supplied to a video display terminal on which the video picture corresponding thereto is formed. The computer program can then be altered, thereby altering the picture, until a satisfactory result is achieved. The final program can then readily be translated into a picture, until a satisfactory result is achieved. The final program can then readily be translated into a system block diagram of standard signal processing blocks, which in turn can be converted into logic code for fabrication of an integrated circuit which will provide signal processing corresponding to the algorithm carried out by the computer program.
The prior art teaches to achieve such simulation on the basis of one or only a few of the time-sequential images which form the video picture, but this does not take into account temporal effects which may result from the processing algorithm. For simulation of both spatial and temporal effects it is necessary to operate in real time, using all of the successive video images. However, real time simulation of the effect of sophisticated processing algorithms on complex video signals, such as those in accordance with NTSC or proposed HDTV standards, would necessitate super-computer performance. This problem has been approached by employing a multiprocessor architecture, using a sufficient number of processors operating in parallel so as to achieve a very high processing rate.
A known type of such a real time multiprocessor video simulator architecture is the "Princeton Engine" developed by the David Sarnoff Research Center in Princeton, N.J., which employs up to 2,048 high speed microprocessors operating in parallel (see "The Princeton Engine: A Real-Time Video Simulator", D. Chin et al, IEEE Trans. Computer Electronics, Vol. 34, No. 2, May 1988, p. 285-297). Each processor stage is assigned to a different area of a particular field of the video picture, thereby reducing the amount of data which must be processed by each individual processor. However, since the effect produced in a given area of the image may be influenced by the effect of the processing algorithm in one or more other areas of the image field, such a parallel architecture requires complex programming and many interstage communication channels even though only a few of such channels may actually be required for a particular image field. The system is therefore relatively inefficient.